1. Field of the Invention
The present invention relates to a memory system and a control method for the same, and more particularly to a memory system with an error correction section employing algebra-based error correcting codes and error correcting codes using probability-based repeated calculations, and a control method for the same.
2. Description of the Related Art
In the semiconductor memory field, developments regarding error correcting codes are actively pursued. Among the error correcting codes, a particular focus of attention in recent years is low density parity check codes (hereinafter referred to as “LDPC codes”), which are error correcting codes using probability-based repeated calculations. For LDPC codes, excellent performance approaching a Shannon limit, which is a theoretical limit of code performance, has been reported.
In algebra-based error correction schemes using hard decision codes such as BCH codes and Reed-Solomon (RS) codes that have been widely in practical use, increasing the rate of correctable bit errors involves problems such as an increase in size of a parity portion or a correction circuit. However, the ability of these schemes to reliably correct a certain number of errors or less has been mathematically demonstrated.
On the other hand, for the LDPC codes, which is an error correcting scheme using probability-based repeated calculations, it is difficult to clearly define the correction ability itself of the codes. Error correction may occasionally fail even for a rather few bit errors.
As such, error correction schemes employing a concatenated code using both an LDPC code and a BCH code are known. For example, Ordinance for Standard Transmission Systems for Digital Broadcasting among Standard Television Broadcasting, Etc., Appended Table 39, Error Correction Scheme for Advanced Narrow-band Transmission Digital Broadcasting (related to Article 49, Section 3), based on specifications in Radio Law (Law No. 131 of 1950), Article 38, defines an error correction scheme employing a concatenated code using a BCH code as an outer code and an LDPC code as an inner code.
However, since decoding processing with the LDPC codes is performed by repeating an iteration process as described later, a large number of iteration processes may be performed. This increases the decoding processing time and also increases the power consumption required for the decoding processing.
Furthermore, in an error check and correction (hereinafter referred to as “ECC”) circuit using the LDPC codes, the processing time increases in proportion to the code length. At the same time, not only an iteration process circuit but also a parity check circuit increases in size.
Here, Japanese Patent Application Laid-Open Publication No. 2008-219528 proposes an ECC circuit that omits iteration processes for data having a reliability exceeding a predetermined value. However, in this ECC circuit, the circuit size increases because parallel processing of operations requires a plurality of threshold determination circuits for bit node reliability. For example, in a scheme using a regular-type parity check matrix of a 256×256 unit matrix, parallel processing of operations of 256 bit nodes in 256 operation units requires a threshold determination circuit (e.g., a magnitude comparator) for each of all operation units. Therefore, the circuit size significantly increases.
Furthermore, in the above ECC circuit, when the number of iteration processes exceeds a predetermined maximum number of iterations and it is found that the error correction does not converge, the iteration process is again performed by including data having a reliability exceeding the threshold. For example, if the maximum number of iterations is eight, the iteration process is again performed after eight iteration processes are finished, and therefore the processing speed may decrease.